Yiwei Yang (Vickie)

I'm a first-year Computer Science System Ph.D. student @BaskinEng. I'm honored to be advised by Andrew Quinn, and hacking on cutting-edge HW/SW co-design. The goal of my research is to accelerate data access and manipulation on modern heterogeneous architecture and general-purpose processors for diverse workloads across companies utilizing CXL technology. I believe in a hardware-software co-design methodology. The hardware provides specialized acceleration capabilities for common cases without sacrificing heterogeneous processing performance with a better knowledge of workloads, while the software adaptively takes advantage of the hardware by sending semantic hints, and falls back to alternative, slower paths whenever hardware acceleration is not achievable. Assured with my great passion for seeking new knowledge and commercial opportunity and situated in two metropolitans, the San Fransisco Bay area, and Shanghai, I'm proud to learn more, benefit others more, and earn more. Previously, I was an undergraduate @ShanghaiTech, writing ChocoPy-LLVM and researching FM/AISec for Professors Foo, making SCC happen with Shu and researching on PMEM @Toast. For UIUC ReU 2021, I learned Java Flaky Test under supervision of Darko and Wing

fn research_no_failure()->Result < Paper, Error > {
    let output = if cfg!(target_os = "linux") {
        Command::new("qemu-x86_64-system")
        .args(["-smp 6",
             "-numa node,cpus=0-2,memdev=mem0,nodeid=0",
             "-object memory-backend-ram,id=mem0,size=8G",
             "-numa node,cpus=3-5,memdev=mem1,nodeid=1",
             "-object memory-backend-ram,id=mem1,size=8G",
             "-m 16G,slots=4,maxmem=32G",
             "-machine q35,cxl=on",
             "-M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G",
             "-device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1",
             "-device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2",
             "-object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M",
             "-object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M",
             "-device cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-mem0"])
            .output()
            .expect("failed to execute process")
    }
    let paper = Paper::new(output);
    loop{
        asm!("clflush" :: "r" (&paper.iter()) : "rax", "rbx", "rcx", "rdx": "volatile" );
        __atomic_thread_fence(__ATOMIC_SEQ_CST);
        if (paper.is_valid()){
            break;
        }
    }
    Ok(paper)
}