Yiwei Yang (Vickie)


I'm a first-year Computer Science System Ph.D. student @BaskinEng. I'm honored to be advised by Andrew Quinn, and hacking on cutting-edge HW/SW co-design. The goal of my research is to accelerate data access and manipulation on modern heterogeneous architecture and general-purpose processors for diverse workloads across companies utilizing CXL technology. I believe in a hardware-software co-design methodology. The hardware provides specialized acceleration capabilities for common cases without sacrificing heterogeneous processing performance with a better knowledge of workloads, while the software adaptively takes advantage of the hardware by sending semantic hints, and falls back to alternative, slower paths whenever hardware acceleration is not achievable. Assured with my great passion for seeking new knowledge and commercial opportunity and situated in two metropolitans, the San Fransisco Bay area, and Shanghai, I'm proud to learn more, benefit others more, and earn more. Previously, I was an undergraduate @ShanghaiTech, writing ChocoPy-LLVM and researching FM/AISec for Professors Foo, making SCC happen with Shu and researching on PMEM @Toast. For UIUC ReU 2021, I learned Java Flaky Test under supervision of Darko and Wing
fn research_no_failure()->Result < Paper, Error > {
    let output = if cfg!(target_os = "linux") {
        .args(["-smp 6",
             "-numa node,cpus=0-2,memdev=mem0,nodeid=0",
             "-object memory-backend-ram,id=mem0,size=8G",
             "-numa node,cpus=3-5,memdev=mem1,nodeid=1",
             "-object memory-backend-ram,id=mem1,size=8G",
             "-m 16G,slots=4,maxmem=32G",
             "-machine q35,cxl=on",
             "-M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G",
             "-device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1",
             "-device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2",
             "-object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M",
             "-object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M",
             "-device cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-mem0"])
            .expect("failed to execute process")
    let paper = Paper::new(output);
        asm!("clflush" :: "r" (&paper.iter()) : "rax", "rbx", "rcx", "rdx": "volatile" );
        if (paper.is_valid()){



Ph.D. Student in Computer Science and Engineering

UC Santa Cruz, California
Santa Cruz, California
July 2022 - July 2028

BEng in Computer Science and Engineering

Shanghaitech, Shanghai
Shanghai, China
September 2018 - July 2022

Industrial Experiences

Serving for HFT team by HPC automated DevOps stack

Jump Trading, Shanghai
Shanghai, China
June 2020 - July 2020
  • High Frequency Trade Order Book simulation applying Linear.Regression Method.
  • Applied salt and jinja to automate scheduling of jobs and assigning affinity of cpu cores in Linux DevOps.
  • Applied eBPF on Distributed Filesystem to try IOVisor stuff.
September 2019 - November 2021
Establish a team of 16 undergraduate students in total for SCC Competition.
  • Profile using Arm Forge/Vtune/Perf, tuning scheduler/MPI affinity/OS params/program parameters
  • Optimize Fortran/C++/Cuda memory/FS MPI/NCCL/Hovorod communication on 2-8 nodes' server
  • Train new members who are interested in system for job-related skills.

Research Interest

  • Memory Forensics
  • Program Analysis
  • File System

Familiar Frameworks

  • RiscV
  • Z3
  • WebAssembly
  • Linux Perf
  • eBPF
  • Gem5
  • MPI
  • iouring

Teaching Assistant

ShanghaiTech CS131: Compiler

UCSC CSE12: Computer Systems and Assembly Language

Research Experiences

Research Assistant
August 2022 - Present
  • Understanding the performance characteristics of CXL.mem systems. Data-driven far memory allocation, prefetching, and replacement policies. Emulating memory disaggregation for data center applications
  • Make Hardware Software Co-design for on CXL.cache data movement
  • Make Virtual Machine migration based on WebAssembly
Research Experiences for Undergraduate
July 2021 - September 2021
Research Assistant Intern
July 2019 - June 2021
  • Researching Adversarial Sample Detection for Deep Neural Familiar Frameworks Network using foolbox and IBM-ART to improve accuracy of object recognition to prevent impostors from hacking into systems.
  • Researching MOVE language in Libra currency source code to protect against Arithmetic Overflow, Timestamp Dependency with LeaferX.
  • Understanding the real access mechanism of Memory Mode Optane Memory and XPBuffer by reverse-engineering methods.


CXLMemSim: A pure software simulated CXL.mem for performance characterization

Critique of "A Parallel Framework for Constraint-Based Bayesian Network Learning via Markov Blanket Discovery" by SCC Team from ShanghaiTech University

Critique of “MemXCT: memory-centric X-ray CT reconstruction with massive parallelization” by SCC Team from ShanghaiTech University

Attack as Defense: Characterizing Adversarial Examples using Robustness