1.
Intro
2.
c艹
2.1.
view
2.2.
pmr
2.3.
static replex expr
3.
Kernel mm
3.1.
cgroup
3.2.
rcu
3.3.
disaggregation
4.
Kernel Obervability
4.1.
record and replay
4.2.
perf
4.3.
instrument
4.4.
eBPF
5.
LLM for Sys for LLM
5.1.
llm z3
6.
RTL
6.1.
Delay buffer
6.2.
Fabric manager
7.
LLVM and MLIR
7.1.
Remotable Pointer
7.2.
MLIR
7.3.
Custom Pass
8.
PCIe CXL
8.1.
NoC
8.2.
PCIe
8.3.
Simulator Design
9.
Rust
9.1.
IORing Windows
9.2.
Asahi Virt
9.3.
LibCapstone
10.
WASM
10.1.
AoT and JIT
10.2.
Linear Memory
11.
Quantitative Approach: A Yiwei's perspective
11.1.
Why not RVV?
11.2.
Why not TPU?
11.3.
What's ROB?
12.
M3 chip explainer
12.1.
GPU
12.1.1.
Register File
12.2.
CPU
12.2.1.
CPU
12.3.
Neural Engine
12.3.1.
AMX
Light
Rust
Coal
Navy
Ayu
SlugWiki
The partial traces collected
How do we codesign pebs to make it programmable?